Theory

Semiconducting carbon nanotubes are envisioned to be used as the active ' element in the field effect transistors of tomorrow. The metallic tubes can on the other hand be used as interconnects in integrated circuits which would decrease their size and enable faster computers with a high density of devices. So far, carbon nanotube transistors have shown good characteristics that in some aspects even excel the performance of devices with more conventional materials. One of the major problems for a large scale production is controlling the position of tubes. This issue is addressed in this project by using an electric field to align the carbon nanotubes during growth with thermal CVD. The alignment is possible since the nanotubes polarise and align along the electric field lines. Attempts by other groups to use electric field aligned growth has been successful but no technique has previously been developed to also individually address the nanotubes to create transistors.

Sample Production

The samples used for the field aligned growth are designed to have several micrometer sized gaps between electrodes that apply the electric field across them. A few different designs have been tested and in one of the more successful, the catalyst is separated from the electrodes by a SiO2 barrier which is three times as high as the surrounding structures. This barrier prevents the tubes from short circuiting the gaps during growth and enable individual connections to gaps.

The structures are transferred to the samples by using electron beam and photolithography to write the pattern in a resist that has been spun onto a silicon wafer. The first step is to selectively etch away 300 nm of the oxide that is covering the wafer which creates the SiO2 barriers. The electrode material which is a 100 nm thick film of molybdenum is then deposited using electron gun evaporation and a lift-off leaves structures only where the resist has been exposed. The same procedure is used for the catalyst which is a multilayer film with 10 nm Al2O3 / 1 nm Fe / 0.2 nm Mo. A SEM image of a gap with barriers is shown in Figure 1.

Figure 1: A SEM image of a gap with SiO2 barriers separating the electrodes that apply the electric field from the catalyst strips. The catalyst strips are connected to local pads (not shown) to be able to characterise individual gaps.

CVD growth

The carbon nanotubes are grown by thermal CVD while an external voltage supply connected to the chip apply 10 V. The sample is heated to 900oC in a gas flow of 500 sccm Ar and 100 sccm H2. The growth is performed by changing Ar to 500 sccm of methane for 5 min.

Results

The results show straight carbon nanotubes bridging gaps (see figure 2). Raman spectroscopy show that the tubes have good quality and AFM measurements give an average diameter of 1.58 nm which means that they are most likely single walled.

Figure 2.A SEM image of a straight carbon nanotube bridging a gap.

Electrical measurements are performed on the gaps which have tubes bridging them using the silicon substrate as a back gate to modulate the electronic transport trough the semiconducting tubes. A plot of the current between the source and drain as a function of the applied bias voltage for different gate voltages for a single tube is shown in figure 3. If the source drain bias voltage is kept constant and the gate voltage is swept while measuring the source drain current, the semiconducting behaviour is evident as can be seen in figure 4. The two set of curves are measurement data when the gate voltage is swept up or down so the carbon nanotube transistor displays hysteresis. If several tubes are crossing a gap, the metallic ones can be burned off by applying a high positive gate voltage while increasing the source drain bias voltage. As can be seen in figure 5, the burning of the tubes is manifested in sharp drops in the source drain current. After the burning, the remaining tube(s) display semiconducting behaviour.

Figure 3. Current between source and drain vs. applied bias voltage for a single carbon nanotube

Figure 4. Current between source and drain vs. gate voltage for a single semiconducting carbon nanotube

Figure 4. Current between source and drain vs. applied bias voltage with a high gate voltage for a single carbon nanotube. As the current is increased, metallic carbon nanotubes are burned off as seen by the sharp steps of the current.

The carbon nanotube devices do not display very good transistor characteristics but improvements such as to create better electrode-nanotube contacts with some suitable metal or creating top gates with thin insulating oxides would improve their performance.